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Open-source verification frameworks for ASIC, FPGA and SoC FPGA designs offer several important benefits. These include cost savings, transparency (it is easier to understand tool behavior, for instance), flexibility, great community support, interoperability and tool chain support, reproducibility (verification environments can be reproduced by others, for example), auditability and vendor independence.
Here are the open-source verification methodologies supported by Aldec’s Active-HDL and Riviera-PRO tools:
- Open Source VHDL Verification Methodology (OSVVM). This advanced verification methodology defines a VHDL verification framework, verification utility library, verification component library, scripting API, and co-simulation capability that simplifies verification. Using OSVVM it is possible to create a simple, readable, and powerful testbench.
- Universal Verification Methodology (UVM). Originally created by Accellera in 2011 and standardized in 2020 as IEEE 1800.2-2020, UVM has been the de-facto verification methodology for ASIC designs for at least a decade and is now being used on high-density FPGA and SoC FPGA designs. It is an open- source library written in SystemVerilog, and it utilizes the power of object-oriented programming for hardware designs.
- Universal VHDL Verification Methodology (UVVM). This is an open source VHDL verification library and methodology, available on both Github and IEEE Standards Association Open, and is developed in cooperation with the European Space Agency (ESA). As with OSVVM, it allows designers to use the language they already know (i.e., VHDL) and add, step-by-step, the functionality needed for their specific testbench.
- Coroutine co-simulation testbench (cocotb). This is an extremely popular open-source and completely free tool for creating hardware testbenches in Python that can be used to verify designs written in VHDL or Verilog, using your simulator of choice.
- The VUnit open-source unit testing framework for VHDL and SystemVerilog. VUnit provides the necessary functionality for continuous and automated unit testing of HDL code and complements traditional testing methods by promoting a "test early and often" approach through automation.
You can find recorded webinars, demonstration videos and application notes that discuss the above methodologies in our Resources center.
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